Implementation of Digital Filters in Programmable Logic Devices

Recent strides in programmable logic density, speed and hardware description languages (HDL’s) have empowered the engineer with the ability to implement digital signal processing (DSP) functionality within programmable logic devices (PLD’s or FPGA’s). This paper, written for the intermediate DSP engineer or logic designer, begins with an overview of general DSP concepts. Filter design principles as well as specific DSP filter architectures are presented including serial and parallel architectures. Techniques for implementing DSP filters in FPGA’s using VHDL are discussed. Methods of exploiting specific FPGA architectures in order to enhance performance in terms of speed, area and power consumption are presented. Some guidelines are given for evaluating different programmable logic device architectures for DSP designs. The paper culminates with a specific IIR filter design implemented in an FPGA using VHDL. Introduction When implementing a digital filter the embedded system designer is faced with two choices: using a dedicated DSP processor or using a hardware approach with either a programmable logic device (PLD) or ASIC. This paper provides an overview of how digital filters are implemented in programmable logic devices. Implementing digital filters in hardware can have distinct advantages over a dedicated processor approach. As IC processing improves and strives to meet Moore’s Law, programmable logic has improved in both cost and speed, making it a viable alternative for implementing digital filters. Not only have the devices improved but the method of designing with programmable logic has become more efficient with the advent of hardware description languages (HDL). HDL’s offer an alternative to the schematic based approach to logic design, where logic gates or registers are connected in schematic fashion. HDL’s are a text based design entry method that allows the designer to describe the logic function at a higher level of abstraction thereby increasing efficiency. The two primary HDL’s used today are Verilog and VHDL, both IEEE standards. Both of these HDL’s (Verilog /VHDL), can be used to implement digital filters and it is not our intention to argue the relative merits of each language. More specifically, this paper discusses how to implement digital filters in programmable logic using VHDL. Why use Programmable Logic for Digital Filters? Since PLD’s are dedicated hardware, they can achieve significant performance increases over a DSP processor. Other advantages include reduced power consumption. Although dedicated DSP processors offer the most flexibility they can require extra clock cycles compared to a hardware implementation, and this can be power inefficient. Since many embedded systems already have some type of programmable logic on the system, the PLD may have the space available for a digital filter. If this extra logic space is not available, the embedded designer may be faced with porting all the firmware over to a dedicated DSP processor. A better alternative might be to increase the size of the programmable logic device to accommodate a digital filter. If the PLD is already in the data path of the embedded system, the latter approach may be easier than initiating a new hardware design with a dedicated DSP processor. Many embedded systems have both a dedicated DSP processor with a PLD device. In over sampled DSP systems, where the data arrives at a high rate, a PLD can down sample the data prior to the DSP processor. Efficient techniques can be employed to simultaneously accomplish polyphase quadrature demodulation and down sampling [15]. When decimation is required, the PLD can off-load some of these processing tasks by performing both filtering and decimation before data is transferred to the DSP for further processing at a lower sample rate.